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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
582 CHAPTER 12 / MODULE AND BIT-SLICE DEVICES
FIGURE 12.22
Design of a 4-bit slice up/down counter with synchronous parallel load and true hold capability.
(a) Operation table for the J th stage. (b) State diagram for the J th stage. (c) NS logic K-map and
minimum cover obtained from (b) assuming the use of D flip-flops.
logic would be too costly (hardware-wise) to justify a design by this means. A much simpler
approach is to use D flip-flops for the parallel load and true hold capability but convert them
to T flip-flops for the up/down count, all on command of two mode-control inputs. This is
the method that is used in this example.
Shown in Fig. 12.22 are ...
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Publisher Resources

ISBN: 9780126912951