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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
12.3 SYNCHRONOUS BINARY COUNTERS 587
FIGURE 12.27
A divide-by-2
12
(16
3
) up/down binary counter with synchronous parallel load and true hold capability
formed by cascading three 4-bit counters of the type given in Fig. 12.26.
Shown in Fig. 12.27 is a three-stage counter of the former type that can sequence through
16
3
1 = 4095 states. At any point in the operation of the counter, it can be given the
command LD(L) = 1(L) to parallel load a binary word of 12 bits. Then when LD(L) = 0(L),
the counter can hold that number if EN is also inactive EN(H ) = 0(H ), or it can count up or
down from that number if EN(H) = 1(H). The direction of count, of course, ...
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Publisher Resources

ISBN: 9780126912951