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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
632 CHAPTER 13 / ALTERNATIVE SYNCHRONOUS FSM ARCHITECTURES
output-forming logic in Eqs. (13.4) becomes
M =
¯
B
¯
CDV + B
¯
D
N = B
¯
CD
¯
V
P =BC
Q =C
¯
D
, (13.5)
as read from the composite K-map in Fig. 13.16c. This represents an increase of three gates
over that required by Eqs. (13.4). But again, the price to be paid for convenience and for
the reduction in external gate logic is the added state decoder hardware.
13.4 STATE MACHINE DESIGNS CENTERED AROUND A PARALLEL LOADABLE
UP/DOWN COUNTER
For purposes of comparison, it will be interesting to design the same FSMs as in Section 13.3
but now centered around a parallel loadable up/down counter instead of a USR. Shown in
Fig. 13.18a is the “linear state machine” of Fig. 13.13a, but now state coded ...
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Publisher Resources

ISBN: 9780126912951