636 CHAPTER 13 / ALTERNATIVE SYNCHRONOUS FSM ARCHITECTURES
a 4-to-1 MUX is indicated by the compressed EV K-maps in Fig. 13.21a. For this example,
the 8-to-1 MUX will be used. Predictably, there is similarity between Eqs. (13.8) and (13.4).
Shown in Fig. 13.22 is the implementation of the FSM in Fig. 13.20a centered around
the parallel loadable up/down counter of Fig. 12.26. A state decoder is used primarily to
reduce the external gate logic required to generate the four outputs. The choice is made to
implement the count enable and direction controls, EN and D/
¯
U , by using 8-to-1 MUXs
although, in the latter case, discrete logic or a 4-to-1 MUX would make more efficient use
of hardware. An additional gate would be necessary to produce the p-term