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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
646 CHAPTER 13 / ALTERNATIVE SYNCHRONOUS FSM ARCHITECTURES
FIGURE 13.31
Design of the parallel-to-series adder/subtractor controller by the one-hot method. (a) State diagram
for the controller initialized into the 000 state by using the one-hot-plus-zero approach. (b) Symbolic
representation of the fusible bit position patterns for an FPLA programmed to generate the NS and
Mealy output logic in Eqs. (13.15).
(S
1
= 0); the XOR gate is set to complement (CMPL) operand B if subtraction or not if
addition, hence CMPL if (
Add/Sub); counting is begun (CNT); and a completion signal
(FIN) is issued at the end of 8 counts, FIN if (CNT = 8). Notice that the
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Publisher Resources

ISBN: 9780126912951