Skip to Main Content
Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
FIGURE 13.36
Next-state- and output-forming logic for the adder/subtractor controller as obtained from the state
diagram in Fig. 13.35a. (a) NS K-maps and minimum cover for a JK flip-flop design. (b) Output
forming logic showing minimum cover.
FIGURE 13.37
Logic minimum design of the parallel-to-serial adder/subtractor controller of Fig. 13.35a by using JK
flip-flops.
654
13.6 SYSTEM-LEVEL DESIGN 655
PI, c(CNT = 8). Thus, roughly twice as much external hardware and one extra flip-flop
are needed by the one-hot approach for the convenience of reading and implementing ...
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Top-Down Digital VLSI Design

Top-Down Digital VLSI Design

Hubert Kaeslin
Engineering Physics

Engineering Physics

S. Mani Naidu
Analog Integrated Circuit Design, 2nd Edition

Analog Integrated Circuit Design, 2nd Edition

Tony Chan Carusone, David A. Johns, Kenneth W. Martin
Analog Circuit Design Volume Three

Analog Circuit Design Volume Three

Bob Dobkin, John Hamburger

Publisher Resources

ISBN: 9780126912951