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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
PROBLEMS 675
FIGURE P13.6
active high. Use a gate-minimum external logic and plan to initialize the FSM into
the 0000 state. (Hint: Look for XOR patterns in the S
1
and S
0
K-maps.)
13.10 A candy bar vending machine is described in Problem 13.3 and is represented by the
state diagram in Fig. P13.2. Change the state code assignment in the state diagram
as follows:
a 0000 b 0001 c 0011 d 0111
e 0010 f 0110 g 0101
Now design this FSM by using a universal shift register (USR) and a state decoder.
To do this, follow the architecture used for the example in Fig. 13.17. Is an output
holding register necessary? Explain your answer.
13.11 In Fig. P13.7 ...
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Publisher Resources

ISBN: 9780126912951