14.2 THE LUMPED PATH DELAY MODELS FOR ASYNCHRONOUS FSMS 685
14.1.2 Need for Asynchronous FSMs
It is perhaps natural to believe that the data processing in and passage through a sequen-
tial machine must be regulated by some periodic sampling (enabling) function, the system
clock. This, of course, is a requirement of the synchronous sequential machine. But one never
questions the absence of a clock in the combinational logic circuits covered in Chapters 6,
7, and 8, yet these circuits are asynchronous machines of a type — those without feed-
back (i.e., nonsequential). Why then the concern about the need for a clock to regulate
synchronous sequential operations? And when is it advantageous, if ever, to perform se-
quential operations asynchronously? ...