Skip to Main Content
Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
14.2 THE LUMPED PATH DELAY MODELS FOR ASYNCHRONOUS FSMS 685
14.1.2 Need for Asynchronous FSMs
It is perhaps natural to believe that the data processing in and passage through a sequen-
tial machine must be regulated by some periodic sampling (enabling) function, the system
clock. This, of course, is a requirement of the synchronous sequential machine. But one never
questions the absence of a clock in the combinational logic circuits covered in Chapters 6,
7, and 8, yet these circuits are asynchronous machines of a type — those without feed-
back (i.e., nonsequential). Why then the concern about the need for a clock to regulate
synchronous sequential operations? And when is it advantageous, if ever, to perform se-
quential operations asynchronously? ...
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Top-Down Digital VLSI Design

Top-Down Digital VLSI Design

Hubert Kaeslin
Engineering Physics

Engineering Physics

S. Mani Naidu
Analog Integrated Circuit Design, 2nd Edition

Analog Integrated Circuit Design, 2nd Edition

Tony Chan Carusone, David A. Johns, Kenneth W. Martin
Analog Circuit Design Volume Three

Analog Circuit Design Volume Three

Bob Dobkin, John Hamburger

Publisher Resources

ISBN: 9780126912951