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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
700 CHAPTER 14 / ASYNCHRONOUS STATE MACHINE DESIGN AND ANALYSIS
FIGURE 14.16
Implementation of the RET D flip-flop. (a) Implementation showing the intermediate functions, and
indicating the proper position of the fictitious LPD memory elements. (b) The same circuit as in (a)
but with the fictitious LPD memory elements removed and showing the asynchronous PR and CL
override connections (dashed lines).
the output from gate 3 is again 1(H ). Since in either case all three inputs to gate 6 are now
1(H ), its output is 1(L), thereby completing the mixed-rail set output from the flip-flop.
In short, it is the CK input that makes possible a mixed-rail set output ...
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Publisher Resources

ISBN: 9780126912951