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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
14.10 DETECTION AND ELIMINATION OF TIMING DEFECTS 701
FIGURE 14.17
(a) Optimized conversion of the RET D flip-flop in Fig. 14.16b to an RET JK flip-flop. (b) Logic
circuit symbol.
by the logic of Eq. (14.10), there results the optimized RET JK flip-flop and logic circuit
symbol shown in Figs. 14.17a and 14.17b. This logic circuit is equivalent to the 74LS109
JK flip-flop but with the added PR override. Note that an FET JK flip-flop results simply
by adding an inverter to the CK input.
14.10 DETECTION AND ELIMINATION OF TIMING DEFECTS
IN ASYNCHRONOUS FSMs
The preceding sections are intended to be only an introduction to asynchronous FSM design.
Much more must be ...
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Publisher Resources

ISBN: 9780126912951