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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
720 CHAPTER 14 / ASYNCHRONOUS STATE MACHINE DESIGN AND ANALYSIS
FIGURE 14.31
Gate requirements for initializing a logic 0 or a logic 1. (a) Active low output from the sanity circuit.
(b) Active high output from the sanity circuit.
applies to an active high output from the sanity circuit. Generally, an ANDing operation is
required to initialize a logic 0, and an ORing operation is required to initialize a logic 1.
For example, a Sanity(L) = 1(L) = 0(H ) initializes a logic 0 if it is the input to an AND
symbol without input active low indicator bubbles, but initializes a logic 1 if it is the input
to an OR symbol with input active low indicator bubbles, ...
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Publisher Resources

ISBN: 9780126912951