14.17 ANALYSIS OF FUNDAMENTAL MODE STATE MACHINES 741
3. Both PLA and PAL implementations can be initialized into an all-zero state by adding
a sanity input to each p-term as shown in Fig. 14.32a. If it is necessary to initialize
a PLA or PAL into an all one state, introduce each y-variable as a separate p-term
and connect Sanity(H ) to it. Obviously, it is easier to initialize 1’s than 0’s in a
NAND-centered PLD. The reverse is true for a NOR-centered PLD.
4. Whereas FPGAs are attractive PLDs for synchronous FSM design, they can be
a source of almost limitless consternation to the designer if used carelessly for
fundamental mode FSM design. The reason for this lies in the fact that routing delays
can seriously alter the timing behavior of asynchronous ...