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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
758 CHAPTER 14 / ASYNCHRONOUS STATE MACHINE DESIGN AND ANALYSIS
the designer might be prudent to include some counteracting delay on specific feedback
lines to further ensure that these timing defects will never occur. Modern logic circuits are
now commonly constructed of very high-speed logic. If, for example, gate propagation de-
lays exist in the subnanosecond range, it does not take much of a lead delay in a specific path
to activate an E-hazard. Such delays may be caused by parasitic capacitance and resistance,
by buffers, or by gates that have abnormally large path delays.
FURTHER READING
Unfortunately, significant reference material in the area of asynchronous state machines
design and analysis is limited to a few text sources. Only the texts
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Publisher Resources

ISBN: 9780126912951