15.3 OTHER CHARACTERISISTICS OF PLUSE MODE FSMs 777
where t
j
represents the feedback delays. The “best case path delay through the system”
is a quantity that usually falls in the range of 2τ
p
to 3τ
p
for most systems, where τ
p
is
an average gate path delay. The lower limit is, as before, the requirement that the pulse
be of sufficient strength to initiate a state change. This lower limit together with the upper
limit expressed by Eq. (15.2) lead to what is called a bounded pulse. The bounded pulse
requirement places a severe restriction on the pulse widths that a nested cell design can
properly accept without malfunction. It is for this reason that the nested cell approach to
pulse mode FSM design is of little or no practical importance. Should the nested ...