Skip to Main Content
Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
15.3 OTHER CHARACTERISISTICS OF PLUSE MODE FSMs 777
where t
j
represents the feedback delays. The “best case path delay through the system”
is a quantity that usually falls in the range of 2τ
p
to 3τ
p
for most systems, where τ
p
is
an average gate path delay. The lower limit is, as before, the requirement that the pulse
be of sufficient strength to initiate a state change. This lower limit together with the upper
limit expressed by Eq. (15.2) lead to what is called a bounded pulse. The bounded pulse
requirement places a severe restriction on the pulse widths that a nested cell design can
properly accept without malfunction. It is for this reason that the nested cell approach to
pulse mode FSM design is of little or no practical importance. Should the nested ...
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Top-Down Digital VLSI Design

Top-Down Digital VLSI Design

Hubert Kaeslin
Engineering Physics

Engineering Physics

S. Mani Naidu
Analog Integrated Circuit Design, 2nd Edition

Analog Integrated Circuit Design, 2nd Edition

Tony Chan Carusone, David A. Johns, Kenneth W. Martin
Analog Circuit Design Volume Three

Analog Circuit Design Volume Three

Bob Dobkin, John Hamburger

Publisher Resources

ISBN: 9780126912951