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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
15.4 DESIGN EXAMPLES 779
as in synchronous FSMs. An existing ORG must be eliminated by altering the state code
assignments to remove the race condition causing the ORG. Static hazards can be eliminated
only by adding hazard cover as in Section 11.3.
15.4 DESIGN EXAMPLES
In this section three pulse mode FSMs of varying complexity will be designed by using
toggle modules as memory elements and will feature different implementations of the NS
and output forming logic. For this purpose use will be made of discrete logic, a ROM, and
a PLA.
A Simple Pulse Mode Sequence Recognizer. Consider the state diagram for a sim-
ple sequence recognizer in Fig. 15.5a
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Publisher Resources

ISBN: 9780126912951