Skip to Main Content
Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
806 CHAPTER 16 / EXTERNALLY ASYNCHRONOUS/INTERNALLY CLOCKED
that drive the sequencer are easily programmed directly from a state diagram or state table,
or from K-maps plotted from the state diagram.
16.2 EXTERNALLY ASYNCHRONOUS/INTERNALLY CLOCKED
SYSTEMS AND APPLICATIONS
The general (Mealy) model for an EAIC system is shown in Fig. 16.1. It consists of input
(synchronization) and memory DFLOP registers of either the static logic (SL) or dynamic
logic (DL) type, next-state-forming logic, and clock-generating circuitry. On the rising edge
of each clock cycle, the inputs are stored in the input register and a new state is stored in
the memory register ...
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Top-Down Digital VLSI Design

Top-Down Digital VLSI Design

Hubert Kaeslin
Engineering Physics

Engineering Physics

S. Mani Naidu
Analog Integrated Circuit Design, 2nd Edition

Analog Integrated Circuit Design, 2nd Edition

Tony Chan Carusone, David A. Johns, Kenneth W. Martin
Analog Circuit Design Volume Three

Analog Circuit Design Volume Three

Bob Dobkin, John Hamburger

Publisher Resources

ISBN: 9780126912951