Skip to Main Content
Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
16.2 EXTERNALLY ASYNCHRONOUS/INTERNALLY CLOCKED SYSTEMS 811
FIGURE 16.7
PSPICE simulation of the static logic MDS circuit in Fig. 16.4b.
on the MDS outputs, y
1
and y
0
. However, the formation of these erroneous output pulses is
very small and directly dependent on the frequency of oscillation. An increase in oscillation
frequency results in a decrease in straddling time and consequently permits the MDS to
correctly filter the metastable condition. In addition, because a valid output pulse can only
be generated if the inputs straddle the adjusted switching threshold, any input activity above
the threshold of 1.1 volts cannot result in output pulses
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Top-Down Digital VLSI Design

Top-Down Digital VLSI Design

Hubert Kaeslin
Engineering Physics

Engineering Physics

S. Mani Naidu
Analog Integrated Circuit Design, 2nd Edition

Analog Integrated Circuit Design, 2nd Edition

Tony Chan Carusone, David A. Johns, Kenneth W. Martin
Analog Circuit Design Volume Three

Analog Circuit Design Volume Three

Bob Dobkin, John Hamburger

Publisher Resources

ISBN: 9780126912951