16.2 EXTERNALLY ASYNCHRONOUS/INTERNALLY CLOCKED SYSTEMS 821
system, externally for the conventional approach. For reference purposes, the following are
examples of the overlap between the two approaches:
1. DFLOPs can be converter to either TFLOPs or JKFLOPs, as is done for D flip-flops
in Section 10.8.
2. The design and analysis of FSMs by using the EAIC system follows the discussion
for synchronous FSMs in Sections 10.12, 10.13, and 11.9.
3. Logic noise (including ORGs and static hazards) in the output functions of EAIC
FSMs can be filtered by using conventional edge triggered D flip-flops as discussed
in Subsection 11.2.2. In contrast to synchronous FSMs, the filtering D flip-flops should
be triggered in phase to the internal clock.
4. Sanity circuits and ...