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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
844 CHAPTER 16 / EXTERNALLY ASYNCHRONOUS/INTERNALLY CLOCKED
this reference, a comparison is made between the EAIC system featured in this chapter and
the Q-Flops described in the article by Rosenberger et al. (cited previously). The part of this
chapter, describing a unique class of asynchronous sequencers (MAC modules), is based in
part on the work of Tinder, Klaus, and Snodderley, cited below. There is no known previous
work on the subject of one-hot programmable asynchronous sequencers. For information
on one-hot asynchronous FSM design, refer to Further Reading at the end of Chapter 14.
[16] W. S. VanScheik and R. F. Tinder, “High Speed Externally Asynchronous/Internally Clocked
Systems,” IEEE Trans. Computers 46(7), 824–829 (1997).
[17] R. F
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Publisher Resources

ISBN: 9780126912951