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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
878 INDEX
Parallel-to-serial adder/subtractor system
Controller, 645–648, 652–655
Design, 651–655
Functional partition, 651–652
Timing diagram, 653
Parity bit, 273
Parity generators and detectors
Design, 273–274
Use of in error checking systems, 274–275
Partitioning method for state code assignments,
721–723
Procedure, 721–722
π-partitions, 721–722
Seed sets, 722–723
τ -partitions, 722
Part numbering systems
CMOS and TTL logic families, 241
ECL logic family, 241
Parasitic capacitance effects, 517
Passive switching devices, 84, 278
Pass transistor switches, 84–85 (see also
transmission gates)
Pausable clock systems
Externally asynchronous/internally clocked
(EAIC) systems, 806–823
PDP, 240 (see also Power-delay product)
Performance characteristics of IC logic families ...
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Publisher Resources

ISBN: 9780126912951