INDEX 883
Timing defects in combinational logic
Dynamic hazards, 392, 409–411
Functional hazards, 392, 412
Static hazards in two-level logic circuits, 392–398
Static hazards in multilevel XOR-type circuits,
399–409
Timing Designer Professional, 586–587
Timing diagrams (examples), 410, 443, 448, 464,
548, 657, 694, 718, 751, 780, 793, 840
Timing problems
In latches, 461–462
In master-slave JK flip-flops, 462–463
Toggle modules
Design from D flip-flops, 573
Use in counter design, 600–605, 664–665
Use in pulse mode FSMs, 773–775
Traffic light control system, 681–682
Transistor-transistor logic (TTL), 850–852
Transmission gates
CMOS, 84–85
Circuit symbols, 84–85
Ideal equivalent circuits, 84–85
NMOS, 84–85
PMOS, 84–85
Transparent D latch. See D-latch
Tree structures, 90, 180 ...