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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
3.4 LOGIC LEVEL CONVERSION: THE INVERTER 83
FIGURE 3.5
Proper PMOS and NMOS placement for generalized CMOS gate configurations.
LV well but not HV. Conversely, PMOS passes HV well but not LV. The proper placement of
the NMOS and PMOS sections results in a sharp, relatively undistorted waveform. Inverting
this configuration would require that the NMOS and PMOS sections pass voltage levels
that they do not pass well, resulting in a distortion of the voltage waveform. Therefore, the
PMOS section is always placed on the HV end with the NMOS on the LV side, as in Fig. 3.5.
3.4 LOGIC LEVEL CONVERSION: THE INVERTER
When a positive logic source is converted
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Publisher Resources

ISBN: 9780126912951