
98 CHAPTER 3 / BACKGROUND FOR DIGITAL DESIGN
FIGURE 3.24
Logic realizations of the function Z (L) with inputs A(H), B(H), C(H), D(L), and E(L). (a) NAND/
NOR/INV logic. (b) AND/OR/INV.
logic in (b). In this example the ORing input stages receive inputs that are assumed to
arrive as A(H), B(H), C(H), D(L), and E(L). Here again, by complementing between the
AND and OR stages (dotted boxes), the physical realization is changed without altering
the original function. Notice that incompatibilities exist on inputs and between ORing and
ANDing stages requiring (in each case) complementation of the signal name in the output
expression as indicated by the “/ ...