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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
152 CHAPTER 4 / LOGIC FUNCTION REPRESENTATION AND MINIMIZATION
AB
CD
00
01
11
10
00
01
1011
A
B
D
C
10
AB
CD
00
01
11
10
00
01
1011
A
B
D
C
45 67
89 1011
12 13 15
01 23
1
0
0
0
00
0
0
0
Y
POS
A
+
C
+
D
B
A
+
D
BCD
(a)
(b)
AD
φ
φ
φφ
Y
SOP
8911
14
457
12
89
11
13 1415
013
6
2
0
0
0
0
11
11
0
0
0
φ
φ
φφ
0
11
1
ABD
FIGURE 4.20
K-maps for Eq. (4.30) containing don’t cares showing (a) minimum POS cover and (b) minimum
SOP cover containing OPIs for minterms in cells 7 and 13 but not shown.
(connections) to gates. Gate tallies are weighted more heavily than input tallies. Inverters
can be included in the gate/input tally of a given function only if the activation levels of the
inputs are known. Unless otherwise stated, the gate/input tallies ...
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Publisher Resources

ISBN: 9780126912951