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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
158 CHAPTER 4 / LOGIC FUNCTION REPRESENTATION AND MINIMIZATION
FIGURE 4.27
NOR/INV logic circuit for the optimized POS system of Fig. 4.25.
making use of all shared PIs in the table of Fig. 4.26a together with the required additional
p-term cover yields a combined gate/input tally of 7/22.
Comparing the POS and SOP results with optimum system covers of cardinality 4 and
5, respectively, it is clear that the POS result is the more optimum (gate/input tally of
6/15 or 10/19 including inverters). Shown in Fig. 4.27 is the optimal NOR/INV logic
implementation of the POS results given by Eqs. (4.37).
The simple search method used here to obtain optimum
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Publisher Resources

ISBN: 9780126912951