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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
CHAPTER 5
Function Minimization
by Using K-map XOR Patterns
and Reed–Muller
Transformation Forms
5.1 INTRODUCTION
In this chapter it will be shown how simple “pencil-and-paper” methods can be used to
extract gate-minimum multilevel logic designs not yet possible by any conventional method,
including the use of CAD techniques. The methods described here make possible multilevel
IC designs that occupy much less real estate than would be possible for an equivalent two-
level design, and often with little or no sacrifice in speed an advantage for VLSI design.
There are a variety of approaches to logic function minimization, which can be divided
into two
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Publisher Resources

ISBN: 9780126912951