198 CHAPTER 5 / FUNCTION MINIMIZATION
device, meaning two units of path delay as implied by the defining relations for XOR and
EQV given by Eqs. (3.4) and (3.5). But the emergence of CMOS IC technology has moved
the XOR and EQV gates close to single-level gates with respect to compactness and speed,
as is evident from Figs. 3.26 and 3.27. The term multilevel, as used in this text, means the
use of XOR and/or EQV gates together with two-level logic to form multiple levels of path
delay as measured from input to output.
The concept of minimization, as used in this text, is presented in terms of three degrees.
A minimum result is one that yields the lowest gate/input tally for a particular method used,
for example, a two-level minimum result, but may