Skip to Content
Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
204 CHAPTER 5 / FUNCTION MINIMIZATION
Table 5.1 Gate/input tallies including inverters for functions E, F, G, H, I,
and J represented as multilevel logic forms and as two-level logic forms
Function EF G H I J
Multilevel 2/44/75/13 7/14 8/15 12/36
Two-level 7/13 7/14 11/21 12/36 12/35 20/81
are a type of timing defect that will be discussed at length in Chapter 9. The term fan-in
refers to the number of inputs required by a given gate. For logic families such as CMOS,
propagation delay is increased significantly with increasing numbers of gate inputs, and it
is here where the multilevel XOR forms often have a distinct advantage over their two-level
counterparts. ...
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

The Electrical Engineering Handbook

The Electrical Engineering Handbook

Wai Kai Chen
Analog Integrated Circuit Design, 2nd Edition

Analog Integrated Circuit Design, 2nd Edition

Tony Chan Carusone, David A. Johns, Kenneth W. Martin

Publisher Resources

ISBN: 9780126912951