230 CHAPTER 5 / FUNCTION MINIMIZATION
[4] R. F. Tinder, “Multilevel Logic Minimization by Using K-map XOR Patterns,” IEEE Trans. on
Ed. 38(4), 370–375 (1995).
Earlier work on Reed–Muller expansions and the use of conventional K-map methods
to obtain Reed–Muller coefficient values can be found in the work of Dietmeyer and Wu
et al.
[5] D. L. Dietmeyer, Logic Design of Digital Systems. Allyn and Bacon, 1978 (Chapter 2).
[6] X. Wu, X. Chen, and S. L. Hurst, “Mapping of Reed–Muller Coefficients and the Minimization
of Exclusive-OR Switching Functions,” Proc. IEE, Part E, 129, 15–20 (1982).
An excellent experimental study of the various XOR and EQV (XNOR) CMOS gate
configurations can be found in the work of Wang, Fang, and Feng.
[7] J. Wang, S. Fang, and W