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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
6.8 COMBINATIONAL SHIFTERS 275
generator module of Fig. 6.33 with an XOR gate and inverter as the output stage, hence an
EQV gate, as implied in Fig. 6.34.
The parity checking scheme illustrated in Fig. 6.34 is valid for the detection of a single
error in the 8-bit word. Actually, it is valid for any odd number of errors, but the probability
that three or more errors will occur in a given word is near zero. What a single-bit parity
checking system cannot do is detect an even number of errors (e.g., two errors). It is also true
that the error checking system of Fig. 6.34 cannot correct any single error it detects. To do
so would require detecting its ...
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Publisher Resources

ISBN: 9780126912951