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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
6.10 INTRODUCTION TO VHDL DESCRIPTION OF COMBINATIONAL PRIMITIVES 279
a considerable savings in transistor count and design area, as indicated in Fig. 6.39b. Here,
the MUX is enabled and buffered by using a tri-state driver with an active low control input.
Thus, the disable condition [EN(L) =0(L)] is actually a disconnect state as indicated in
Fig. 3.8b and is represented by the dash in the truth table of Fig. 6.39a. Notice that the AND
plane, equivalent to the four four-input NAND gates in Fig. 6.4d, is constructed with only
eight transmission gates, and that the OR operation is “wired” to the tri-state driver since
only one line can be active
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Publisher Resources

ISBN: 9780126912951