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Engineering Digital Design
book

Engineering Digital Design

by Richard F. Tinder
January 2000
Intermediate to advanced content levelIntermediate to advanced
884 pages
29h 39m
English
Academic Press
Content preview from Engineering Digital Design
284 CHAPTER 6 / NONARITHMETIC COMBINATIONAL LOGIC DEVICES
architecture structure comp of bit compare is
component inv
generic (tplh, tphl: time); port (i1: in bit; o1: out bit);
end component;
component nand2
generic (tplh, tphl: time); port (i1, i2: in bit; o1: out bit);
end component;
component nand3
generic (tplh, tphl: time); port (i1, i2, i3: in bit; o1: out bit);
end component;
for all:invuse entity avg
delay inv;
for all: nand2 use entity avg
delay nand2;
for all: nand3 use entity avg
delay nand3;
-- Intermediate signals must be declared:
signal im1, im2, im3, im4, im5, im6, im7, im8, im9, im10: bit;
begin
a
gt b output
gate1: inv generic map (tplh, tphl) ...
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Publisher Resources

ISBN: 9780126912951