Book description
Shows readers how to gain the competitive edge in the integrated circuit marketplace
This book offers a wholly unique perspective on the digital design kit. It points to hidden value in the safety margins of standard-cell libraries and shows design engineers and managers how to use this knowledge to beat the competition.
Engineering the CMOS Library reveals step by step how the generic, foundry-provided standard-cell library is built, and how to extract value from existing std-cells and EDA tools in order to produce tighter-margined, smaller, faster, less power-hungry, and more yield-producing integrated circuits. It explores all aspects of the digital design kit, including the different views of CMOS std-cell libraries along with coverage of IO libraries, memory compilers, and small analog blocks. Readers will learn:
How to work with overdesigned std-cell libraries to improve profitability while maintaining safety
How functions usually found in std-cell libraries cover the design environment, and how to add any missing functions
How to harness the characterization technique used by vendors to add characterization without having to get it from the vendor
How to use verification and validation techniques to ensure proper descriptive views and even fix inconsistencies in vendor release views
How to correct for possible conflicts arising from multiple versions and different vendor sources in any given integrated circuit design
Complete with real-world case studies, examples, and suggestions for further research, Engineering the CMOS Library will help readers become more astute designers.
Table of contents
- Cover
- Contents
- Title
- Copyright
- Preface
- Acknowledgments
- Chapter 1: Introduction
- Chapter 2: Stdcell Libraries
- Chapter 3: IO Libraries
- Chapter 4: Memory Compilers
- Chapter 5: Other Functions
- Chapter 6: Physical Views
- Chapter 7: SPICE
-
Chapter 8: Timing Views
- 8.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
- 8.2 Performance Limits and Measurement
- 8.3 Default Versus Conditional Arcs
- 8.4 Break-Point Optimization
- 8.5 A Word on Setup and Hold
- 8.6 Failure Mechanisms and Roll-Off
- 8.7 Supporting Efficient Synthesis
- 8.8 Supporting Efficient Timing Closure
- 8.9 Design Corner Specific Timing Views
- 8.10 Nonlinear Timing Views are so “Old Hat” . . .
- 8.11 Concepts for Further Study
-
Chapter 9: Power Views
- 9.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
- 9.2 Timing Arcs Versus Power Arcs
- 9.3 Static Power
- 9.4 Real Versus Measured Dynamic Power
- 9.5 Should Power Be Built as a Monotonic Array?
- 9.6 Best-Case and Worst-Case Power Views Versus Best-Case and Worst-Case Timing Views
- 9.7 Efficiently Measuring Power
- 9.8 Concepts for Further Study
- Chapter 10: Noise Views
- Chapter 11: Logical Views
- Chapter 12: Test Views
- Chapter 13: Consistency
- Chapter 14: Design for Manufacturability
- Chapter 15: Validation
- Chapter 16: Playing with the Physical Design Kit: Usually “At Your Own Risk”
- Chapter 17: Tagging and Revisioning
- Chapter 18: Releasing and Supporting
-
Chapter 19: Other Topics
- 19.1 Lesson from the Real World: The Manager’s Perspective and the Engineer’s Perspective
- 19.2 Supporting High-Speed Design
- 19.3 Supporting Low-Power Design
- 19.4 Supporting Third-Party Libraries
- 19.5 Supporting Black Box Third-Party IP (Intellectual Property) Design
- 19.6 Supporting Multiple Library Design
- 19.7 Concepts for Further Study
- Chapter 20: Communications
- Appendix I
- Appendix II
- Appendix III
- Appendix IV
- Index
Product information
- Title: Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon
- Author(s):
- Release date: May 2012
- Publisher(s): Wiley
- ISBN: 9781118243046
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