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Engineering the Complex SOC: Fast, Flexible Design with Configurable Processors by Chris Rowen

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Chapter 8The Future of SOC Design: The Sea of Processors

In 1965, Dr. Gordon Moore famously observed and codified an exponential growth in the number of transistors per integrated circuit. Engineers now can put entire systems on one integrated circuit as a direct result of Moore’s law scaling. In a generic 130nm standard-cell foundry process, silicon density routinely exceeds 100K usable gates per mm2. Consequently, even a low-cost chip (50mm2 of core area) can carry 5M gates of logic today, and inexpensive chips will likely carry 20M usable gates by 2007. This density increase has been consistently matched by improvements in power dissipation, circuit speed, and system form factor. Silicon scaling creates an enormous range of design opportunities, ...

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