ESD

5Analog and ESD Design Synthesis

5.1 Early ESD Failures in Analog Design

In early development of semiconductor chips, the concepts for implementing analog circuitry on semiconductor chips with other circuitry and providing electrostatic discharge (ESD) protection were not well understood [1–10, 12–18]. Through significant years of ESD design solution, the ESD design synthesis evolved to where it is today [11–18]. In this chapter, examples and case studies of ESD failure in early architecture concepts will be discussed to provide the reader with some historical background and provide insight into the issues that occur in domain separation. The chapter will then discuss the modern-day issues in the present analog architecture.

5.2 Mixed-Voltage Interface: Voltage Regulator Failures

An early example of voltage regulator ESD failures, in the 1990s, was evident in DRAM applications that required the internal core voltage to be lower than the peripheral circuits [15–17]. In this architecture, the peripheral circuit had a separate power rail and ground distinct from the core power rail and the core ground. Figure 5.1 shows an architecture of the external circuitry and core circuits. Peripheral I/O circuitry would have ESD protection circuits that would be electrically connected to the peripheral I/O power rail [15]. The peripheral I/O power rail was isolated from the core power rail by a voltage regulator. Two different versions of the voltage regulator were implemented.

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