12Analog ESD and Latchup Design Rule Checking and Verification

In this chapter, the focus is on electronic design automation (EDA) associated with electrical overstress (EOS) design. This continues to be a growing issue, as new concepts and techniques are developed. In this chapter, electrostatic discharge (ESD) concepts will also be highlighted due to the similarity of concepts for both EOS and ESD EDA. Latchup electronic design automation (EDA) techniques relevant to EOS issues will also be shown.

12.1 Electronic Design Automation

EDA is a software tool specifically for the design of electronic systems such as single components, integrated circuits, and printed circuit boards (PCBs). EDA tools can be applied to ESD [1–28], EOS [25], latchup [11, 29–54], and other electromagnetic compatibility (EMC) issues. In this chapter, the focus will be on how EDA and computer-aided design (CAD) can be utilized to provide more robust electronic systems addressing whole-chip analysis and cross-domain issues in mixed-signal (MS) system-on-chip (SOC) applications [23, 55–69]. Figure 12.1 is an example of the checking and verification needs today in an EOS environment.


Figure 12.1 Checking and verification.

12.2 Electrical Overstress (EOS) and ESD Design Rule Checking

EOS and ESD design rules will be discussed in this section [1–3]. As new problems and issues arise in integrated circuits and SOC applications, ...

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