5.1 Early ESD Failures in Analog Design5.2 Mixed-Voltage Interface: Voltage Regulator Failures5.3 Separation of Analog Power from Digital Power AVDD to DVDD5.4 ESD Failure in Phase Lock Loop (PLL) and System Clock5.5 ESD Failure in Current Mirrors5.6 ESD Failure in Schmitt Trigger Receivers5.7 Isolated Digital and Analog Domains5.8 ESD Protection Solution: Connectivity of AVDD to VDD5.9 Connectivity of AVSS to DVSS5.10 Digital and Analog Domain with ESD Power Clamps5.11 Digital and Analog Domain with Master/Slave ESD Power Clamps5.12 High-Voltage, Digital, and Analog Domain Floor Plan5.13 Closing Comments and SummaryReferences