6.2. What Is Design Synthesis?
The FPGA device consists of logic blocks or cells that are configured to perform the functions defined by the high-level design. So far, all we have is a high-level design but nothing that associates it with the internal FPGA resources. Design synthesis or synthesis is the process that takes the high-level design associates it with FPGA resource and reduces logic to make the design more efficient. It can best be described as a three-step process that converts a high-level design to a mid-level design netlist, see Figure 6-2. The reason I say mid-level design netlist is because it cannot be used to program an FPGA, but it is just one development stage from being ready to burn into a chip. Synthesis is the first ...
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