O'Reilly logo

FPGAs für Maker by Cord Elias

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

A VHDL-Kurzübersicht

A.1 entity

entity demo_entity is  generic  (    g_limit : integer := 128;    g_ledcount : integer := 4  );  port  (    clk_i : in std_logic;    reset_i : in std_logic;    leds_o : out std_logic_vector(g_ledcount-1 downto 0)  );end demo_entity;

Beachten:

  • Letzter Eintrag Generic-Liste ohne Semikolon

  • Letzter Eintrag Port-Liste ohne Semikolon

  • Generic- und Port-Liste jeweils in runden Klammern, Abschluss mit Semikolon

A.2 architecture

architecture <arch-name> of <entity-name> iscomponent <component-name> is...end component;signal abc : unsigned(3 downto 0);begin  mycomp : <component-name>  port map  (   ...  );  process (clk)  begin   ...  end process;  sout <= abc;  ...end <arch-name>;

Beachten:

  • <arch-name> kann beliebig gewählt ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required