GeOI as a Platform for Ultimate Devices
IMEP-LAHC/Minatec, Grenoble-INP, 3 parvis Louis Néel, Grenoble, France
CEA-LETI/Minatec, F38014, Grenoble, France
Div. of Engineering, Brown University, Providence, RI 02912, U.S.A.
The International Roadmap for Semiconductors predicts increasing device and circuit performance through the reduction of the physical MOSFET gate length for years to come.1 At the same time, the supply voltage VDD will also continue to decrease, whereas the dynamic power consumption has to be limited to around 100 W/cm2 for the future Si technology nodes (< 45 nm). Hence, a strong enhancement of the transport properties is the key point for reliable future nodes. The on-state current ION of the MOSFETs is intrinsically linked and limited by the active semiconductor material, in particular for short-channel technologies where ballistic transport appears. Besides the incremental technological booster solutions for silicon CMOS (source-drain engineering, SOI, strained SOI, etc.), there is a strong research effort to conceive of new architectures, like the 3D stacking,2 or to replace silicon-based channels with higher mobility materials.
Germanium had been used decades ago to create the first generation of field effect and bipolar transistors. Unfortunately, the poor quality of its native oxide (GeO2) made it unsuitable for VLSI. However, the ...