Silicon-Based Devices and Materials for Nanoscale CMOS and Beyond-CMOS

F. Balestra

Sinano Institute, IMEP-Minatec, CNRS-Grenoble INP 3 Parvis Louis Née!, BP 257, 38016 Grenoble, France

1.   Introduction

The minimum critical feature size of the elementary devices (physical gate length LG of the transistors) will drop from 25 nm in 2007 (65 nm technology node) to 4.5 nm in 2022 (11 nm technology node). In the sub-10nm range, beyond-CMOS devices will certainly play an important role and could be integrated on CMOS platforms in order to pursue integration down to nm structures. While Si will remain the main semiconductor material for the foreseeable future, the needed performance improvements for the end of the ITRS Roadmap1,2 will substantially expand the number of materials, technologies and device architectures.

Silicon-on-insulator (SOI)-based devices seem to be the best candidates for the ultimate integration of integrated circuits on silicon.3,4 An overview of the main advantages of SOI for the nanoelectronics of the next two or three decades is presented in this chapter. We will consider nanoscale CMOS, emerging and beyond-CMOS nanodevices, based on innovative concepts, technologies and device architectures. The flexibility of the SOI structure enables new device architectures that can be used to optimize electrical properties for both low-power and high-performance circuits. These transistors are also promising for high frequency and memory applications. We will discuss the ...

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