
Power Efficient Architectures for Router Functions 205
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Reduced power in percentage (%)
Figure 7.10: Reduced power vs. the number of queues.
can be very small [3] and the buffer size can be reduced to 20-50 packets if we
are willing to sacrifice a fraction of link capacity, and if there is a large ratio
between the speed of core and access links. Therefore the TM can utilize a
small-size on-chip memory to buffer the packets most of the time, and activate
the off-chip memory to store the packets only when the on-chip memory is
about to overflow. In such a design, the off-chip memory and its corresponding ...