Handbook of 3D Integration, Volume 4

5Physical Design Flow for 3D/CoWoS® Stacked ICs

Yu‐Shiang Lin Sandeep K. Goel¹ Jonathan Yuan Tom Chen and Frank Lee

Taiwan Semiconductor Manufacturing Company Ltd., Design Technology Platform, 2585 Junction Ave, San Jose, CA, 95134, USA

5.1 Introduction

Traditional 2D‐IC has been riding on the scaling of the Moore's law to become more powerful within the same footprint in the last few decades. However, it is becoming harder and harder to maintain this trend of doubling the number of transistors every 18 months. It is not only becoming more challenging to manufacture transistors at smaller dimensions but also getting harder to sustain the overall system performance improvement on all front. For example, the requirement of memory bandwidth needs ...