Chapter 13Optimization of Test‐Access Architectures and Test Scheduling for 3D ICs
Sergej Deutsch1, Brandon Noia1, Krishnendu Chakrabarty1, and Erik Jan Marinissen2
1 Duke University, Department of Electrical and Computer Engineering, Durham, NC, 27708, USA
2 IMEC, Kapeldreef 75, 3001, Leuven, Belgium
An undesirable outcome of the potential of 3D stacks to integrate a number of large system‐on‐chips (SoCs) is that the complexity and cost of test are increased. Therefore, 3D test requires careful attention in order to optimize test cost. Recent work on 3D test strategies has addressed this issue and presented several methods for test architecture optimization and test scheduling. These methods are based on exact optimization techniques such as ...
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