Hardware Design Verification: Simulation and Formal Method-Based Approaches

Chapter 1. An Invitation to Design Verification

Chapter Highlights

• What is design verification?

• The basic verification principle

• Verification methodology

• Simulation-based verification versus formal verification

• Limitations of formal verification

• A quick overview of Verilog scheduling and execution semantics

From the makeup of a project team, we can see the importance of design verification. A typical project team usually has an equal number of design engineers and verification engineers. Sometimes verification engineers outnumber design engineers by as many as two to one. This stems from the fact that to verify a design, one must first understand the specifications as well as the design and, more important, devise a different design approach from the ...