Chapter 1. Technical description 17
1.6 IBM XceL4 Server Accelerator Cache
Integrated into the processor-board assembly is 64 MB of Level 4 cache, which is
shown in Figure 1-1 on page 4. This XceL4 Server Accelerator Cache provides
the necessary extra level of cache to maximize CPU throughput by reducing the
need for main memory access under demanding workloads, resulting in an
overall enhancement to system performance.
Cache memory is two-way interleaved 200 MHz DDR memory and is faster than
the main memory because it is directly connected to the memory controller and
does not have additional latency associated with the large fan-out necessary to
support the 28 DIMM slots. Since the data interface to the controller is 400 MHz,
peak bandwidth for the XceL4 cache is 6.4 GBps.
1.7 System memory
The x450 has 1 GB or 2 GB of RAM standard, depending on the model. Memory
packaging is PC2100 ECC DDR SDRAM DIMMs, and standard memory is either
two or four 512 MB DIMMs. Memory options are 512 MB, 1 GB, or 2 GB DIMMs.
There are a total of 28 DIMM sockets (two ports of 14). All 28 DIMM sockets can
be used to install DIMMs, with the exception of the 2 GB DIMM option. If 2 GB
DIMMs are installed, the total number of DIMM sockets that can be used is
limited to 20. A maximum of 40 GB of system memory is supported by populating
20 DIMM sockets each with a 2 GB DIMM.
DIMMs must be installed in matched pairs, since the DIMMs are two-way
interleaved. However, if memory is installed in matched fours (a matched pair in
each port), the system automatically detects this and will enable four-way
interleaving. With this, memory access is performed simultaneously from both
ports (two separate paths into the memory controller as shown in Figure 1-1 on
page 4), leading to improved memory performance.
See 3.1.2, “Memory” on page 41 for a further discussion of how memory is
implemented in the x450 and what you should consider before an x450
installation.
There are a number of advanced features implemented in the x450 memory
subsystem, collectively known as
Active Memory:
Restriction: The ability to hot-add or hot-replace memory is not available in
the x450.
18 IBM ^ xSeries 450 Planning and Installation Guide
򐂰 Memory ProteXion
Memory ProteXion, also known as “redundant bit steering”, is the technology
behind using redundant bits in a data packet to provide backup in the event of
a DIMM failure.
Currently, other industry-standard servers use 8 bits of the 72-bit data packets
for ECC functions and the remaining 64 bits for data. However, the x450 uses
an advanced ECC algorithm that is based not on bits but on memory symbols.
Symbols are groups of multiple bits, and in the case of the x450, each symbol
is 4 bits wide. With two-way interleaved memory, the algorithm needs only
three symbols to perform the same ECC functions, thus leaving one symbol
free (2 bits on each DIMM). See Figure 1-10.
Figure 1-10 Memory ProteXion
In the event that a chip failure on the DIMM is detected by memory scrubbing,
the memory controller can re-route data around that failed chip through the
spare symbol (similar to the hot-spare drive of RAID array). It can do this
automatically without issuing a Predictive Failure Analysis® (PFA) or light
path diagnostics alert to the administrator. After the second DIMM failure, PFA
and light path diagnostics alerts would occur on that DIMM as normal.
򐂰 Memory scrubbing
Memory scrubbing is an automatic daily test of all the system memory that
detects and reports memory errors that might be developing before they
cause a server outage.
Memory scrubbing and Memory ProteXion work in conjunction with each
other, but they do not require memory mirroring (as described below) to be
enabled to work properly.
When a bit error is detected, memory scrubbing determines if the error is
recoverable or not. If it is recoverable, Memory ProteXion is enabled and the
data that was stored in the damaged locations is rewritten to a new location.
The error is then reported so that preventative maintenance can be
performed.
As long as there are enough good locations to allow the proper operation of
the server, no further action is taken other than recording the error in the error
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