Chapter 2. System structure and design 31
Figure 2-6 Three-book system ring structure
Figure 2-7 Four-book system ring structure
2.1.5 Connectivity
STI connections to I/O cages and ICB-4 links are driven from the Memory Bus Adapters
(MBAs) that are located on a separate card in the book. Figure 2-8 on page 32 shows the
location of the STI connectors and the MBA card.
STI
MBA
STI
STI STI
STI
MBA
STI
STI STI
4 x 2 GB/S 4 x 2 GB/S
STI
MBA
STI
STI STI
4 x 2 GB/S
MBA Card
Ring Structure
PU PUPUPU PU PU PU PU PU PU PU PU
Jumper Book
STI
MBA
STI
STI STI
STI
MBA
STI
STI STI
4 x 2 GB/S 4 x 2 GB/S
STI
MBA
STI
STI STI
4 x 2 GB/S
MBA Card
PU PUPUPU PU PU PU PU PU PU PU PU
STI
MBA
STI
STI STI
STI
MBA
STI
STI STI
4 x 2 GB/S 4 x 2 GB/S
STI
MBA
STI
STI STI
4 x 2 GB/S
PU PUPUPU PU PU PU PU PU PU PU PU
Memory Up to 64GB
Level 2 Cache 32MB
MCM
MCM
Memory Up to 64GB
Memory Up to 64GB
Level 2 Cache 32MB
Level 2 Cache 32MB
MCM
MCM
MCM
MCM
Ring Structure
STI
MBA
STI
STI STI
STI
MBA
STI
STI STI
4 x 2.5 GB/S 4 x 2.5 GB/S
STI
MBA
STI
STI STI
4 x 2.5 GB/S
MBA Card
STI
MBA
STI
STI STI
STI
MBA
STI
STI STI
4 x 2.5 GB/S 4 x 2.5 GB/S
STI
MBA
STI
STI ST I
4 x 2.5 GB/S
MBA Card
STI
MBA
STI
STI STI
STI
MBA
STI
STI STI
4 x 2.5 GB/S 4 x 2.5 GB/S
STI
MBA
STI
STI STI
4 x 2.5 GB/S
MBA Card
STI
MBA
STI
STI STI
STI
MBA
STI
STI STI
4 x 2.5 GB/S 4 x 2.5 GB/S
STI
MBA
STI
STI ST I
4 x 2.5 GB/S
MBA Card
Memory Up to 64GB
Level 2 Cache 32MB
PU PUPUPU PU PU PU PU PU PU PU PU
MCM
MCM
PU PUPUPU PU PU PU PU PU PU PU PU
PU PUPUPU PU PU PU PU PU PU PU PU PU PUPUPU PU PU PU PU PU PU PU PU
Memory Up to 64GB
Level 2 Cache 32MB
MCM
MCM
Memory Up to 64GB
Level 2 Cache 32MB
MCM
MCM
Level 2 Cache 32MB
Memory Up to 64GB
MCM
MCM
32 IBM ^ zSeries 990 Technical Guide
Figure 2-8 STI connectors and MBA card
Each book has three MBAs, each driving four STIs, resulting in 12 STIs per book.
All 12 STIs per book have a data rate of 2.0 GBps, resulting in a sustained bandwidth of 24
GBps per book. Consequently, the total instantaneous internal bandwidth of a four-book
system is 4 x 24 GBps or 96 GBps. Depending on the channel types installed, a maximum of
512 channels per CPC is currently supported.
Four STIs are related to one MBA. When configuring for availability, you should balance
channels, links, and OSAs across books, MBAs, and STIs. For z990, enhancements have
been made such that, in the unlikely event of a catastrophic failure of an MBA chip, the failure
is contained to that chip, while the other two MBAs on that book continue to operate. In a
system configured for maximum availability, alternate paths will maintain access to critical I/O
devices.
In the configuration reports, books are numbered 0, 1, 2, and 3, MBAs are numbered from 0
to 2, and the STIs are identified as jacks numbered from J.00 to J.11.
Book upgrade
As a result of a concurrent book upgrade, additional MBA and STIs connectors become
available. Since now more external connections to the I/O are potentially available, there may
be circumstances in which it might be beneficial to rebalance the total I/O configuration
across all available MBA/STIs.
Not all book upgrades will necessitate a rebalance of the I/O configuration, since the number
of STIs of the original configuration may well be able to service all existing I/O in an efficient
and balanced way.
However, if the result of the upgrade is an unbalanced I/O configuration, you should consider
rebalancing the configuration by using the additional MBA/STIs. An I/O distribution over
books, MBAs, STIs, I/O cages, and I/O cards is often desirable for both performance and
Book front view
STI connectors
LEDs
S
E
E
P
MBA
MBA
MBA
STI STI STI STI
STI STI STI STI
STI STI STI STI
FGA
VHDM
6-ROW (720 Signal Pins
)
MBA card
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