IBM eX5 Implementation Guide

18 IBM eX5 Implementation Guide

Hyper-Threading Technology is designed to improve server performance by exploiting the

multi-threading capability of operating systems and server applications in such a way as to

increase the use of the on-chip execution resources available on these processors.

Applications types that make the best use of Hyper-Threading are virtualization, databases,

email, Java™, and web servers.

For more information about Hyper-Threading Technology, go to the following website:

http://www.intel.com/technology/platform-technology/hyper-threading/

2.2.3 Turbo Boost Technology

Intel Turbo Boost Technology dynamically turns off unused processor cores and increases the

clock speed of the cores in use. For example, with six cores active, a 2.26 GHz 8-core

processor can run the cores at 2.53 GHz. With only three or four cores active, the same

processor can run those cores at 2.67 GHz. When the cores are needed again, they are

dynamically turned back on and the processor frequency is adjusted accordingly.

Turbo Boost Technology is available on a per-processor number basis for the eX5 systems.

For ACPI-aware operating systems, no changes are required to take advantage of it. Turbo

Boost Technology can be engaged with any number of cores enabled and active, resulting in

increased performance of both multi-threaded and single-threaded workloads.

Frequency steps are in 133 MHz increments, and they depend on the number of active cores.

For the 8-core processors, the number of frequency increments is expressed as four numbers

separated by slashes: the first two for when seven or eight cores are active, the next for when

five or six cores are active, the next for when three or four cores are active, and the last for

when one or two cores are active, for example, 1/2/4/5 or 0/1/3/5.

When temperature, power, or current exceeds factory-configured limits and the processor is

running above the base operating frequency, the processor automatically steps the core

frequency back down to reduce temperature, power, and current. The processor then

monitors temperature, power, and current and re-evaluates. At any given time, all active cores

run at the same frequency.

For more information about Turbo Boost Technology, go to the following website:

http://www.intel.com/technology/turboboost/

2.2.4 QuickPath Interconnect (QPI)

Early Intel Xeon multiprocessor systems used a shared front-side bus, over which all

processors connect to a core chip set, and which provides access to the memory and I/O

subsystems, as shown in Figure 2-1 on page 19. Servers that implemented this design

include the IBM eServer™ xSeries 440 and the xSeries 445.

Chapter 2. IBM eX5 technology 19

Figure 2-1 Shared front-side bus, in the IBM x360 and x440; with snoop filter in the x365 and x445

The front-side bus carries all reads and writes to the I/O devices, and all reads and writes to

memory. Also, before a processor can use the contents of its own cache, it must know

whether another processor has the same data stored in its cache. This process is described

as

snooping the other processor’s caches, and it puts a lot of traffic on the front-side bus.

To reduce the amount of cache snooping on the front-side bus, the core chip set can include a

snoop filter, which is also referred to as a cache coherency filter. This filter is a table that

keeps track of the starting memory locations of the 64-byte chunks of data that are read into

cache, called

cache lines, or the actual cache line itself, and one of four states: modified,

exclusive, shared, or invalid (MESI).

The next step in the evolution was to divide the load between a pair of front-side buses, as

shown in Figure 2-2. Servers that implemented this design include the IBM System x3850

and x3950 (the

M1 version).

Figure 2-2 Dual independent buses, as in the x366 and x460 (later called the x3850 and x3950)

This approach had the effect of reducing congestion on each front-side bus, when used with a

snoop filter. It was followed by independent processor buses, shown in Figure 2-3 on

page 20. Servers implementing this design included the IBM System x3850 M2 and x3950

M2.

Memory I/O

Processor ProcessorProcessor Processor

Core Chip set

Memory I/O

Processor ProcessorProcessor Processor

Core Chip set