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IBM z13s Technical Guide

Book Description

Digital business has been driving the transformation of underlying information technology (IT) infrastructure to be more efficient, secure, adaptive, and integrated. IT must be able to handle the explosive growth of mobile clients and employees. It also must be able to process enormous amounts of data to provide deep and real-time insights to help achieve the greatest business impact.

This IBM® Redbooks® publication addresses the new IBM z Systems™ single frame, the IBM z13s server. IBM z Systems servers are the trusted enterprise platform for integrating data, transactions, and insight. A data-centric infrastructure must always be available with a 99.999% or better availability, have flawless data integrity, and be secured from misuse. It needs to be an integrated infrastructure that can support new applications. It also needs to have integrated capabilities that can provide new mobile capabilities with real-time analytics delivered by a secure cloud infrastructure.

IBM z13s servers are designed with improved scalability, performance, security, resiliency, availability, and virtualization. The superscalar design allows z13s servers to deliver a record level of capacity over the prior single frame z Systems server. In its maximum configuration, the z13s server is powered by up to 20 client characterizable microprocessors (cores) running at 4.3 GHz. This configuration can run more than 18,000 millions of instructions per second (MIPS) and up to 4 TB of client memory. The IBM z13s Model N20 is estimated to provide up to 100% more total system capacity than the IBM zEnterprise® BC12 Model H13.

This book provides information about the IBM z13s server and its functions, features, and associated software support. Greater detail is offered in areas relevant to technical planning. It is intended for systems engineers, consultants, planners, and anyone who wants to understand the IBM z Systems™ functions and plan for their usage. It is not intended as an introduction to mainframes. Readers are expected to be generally familiar with existing IBM z Systems technology and terminology.

Table of Contents

  1. Front cover
  2. Figures
  3. Notices
    1. Trademarks
  4. IBM Redbooks promotions
  5. Preface
    1. Authors
    2. Now you can become a published author, too!
    3. Comments welcome
    4. Stay connected to IBM Redbooks
  6. Chapter 1. Introducing IBM z13s servers
    1. 1.1 Overview of IBM z13s servers
    2. 1.2 z13s servers highlights
      1. 1.2.1 Processor and memory
      2. 1.2.2 Capacity and performance
      3. 1.2.3 I/O subsystem and I/O features
      4. 1.2.4 Virtualization
      5. 1.2.5 Reliability, availability, and serviceability design
    3. 1.3 z13s technical overview
      1. 1.3.1 Models
      2. 1.3.2 Model upgrade paths
      3. 1.3.3 Frame
      4. 1.3.4 CPC drawer
      5. 1.3.5 I/O connectivity: PCIe and InfiniBand
      6. 1.3.6 I/O subsystem
      7. 1.3.7 Parallel Sysplex Coupling and Server Time Protocol connectivity
      8. 1.3.8 Special-purpose features
      9. 1.3.9 Reliability, availability, and serviceability
    4. 1.4 Hardware Management Consoles and Support Elements
    5. 1.5 IBM z BladeCenter Extension (zBX) Model 004
      1. 1.5.1 Blades
      2. 1.5.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
    6. 1.6 IBM z Unified Resource Manager
    7. 1.7 IBM Dynamic Partition Manager
    8. 1.8 Operating systems and software
      1. 1.8.1 Supported operating systems
      2. 1.8.2 IBM compilers
  7. Chapter 2. Central processor complex hardware components
    1. 2.1 Frame and drawers
      1. 2.1.1 The z13s frame
      2. 2.1.2 PCIe I/O drawer and I/O drawer features
    2. 2.2 Processor drawer concept
      1. 2.2.1 CPC drawer interconnect topology
      2. 2.2.2 Oscillator
      3. 2.2.3 System control
      4. 2.2.4 CPC drawer power
    3. 2.3 Single chip modules
      1. 2.3.1 Processor units and system control chips
      2. 2.3.2 Processor unit (PU) chip
      3. 2.3.3 Processor unit (core)
      4. 2.3.4 PU characterization
      5. 2.3.5 System control chip
      6. 2.3.6 Cache level structure
    4. 2.4 Memory
      1. 2.4.1 Memory subsystem topology
      2. 2.4.2 Redundant array of independent memory
      3. 2.4.3 Memory configurations
      4. 2.4.4 Memory upgrades
      5. 2.4.5 Preplanned memory
    5. 2.5 Reliability, availability, and serviceability
      1. 2.5.1 RAS in the CPC memory subsystem
      2. 2.5.2 General z13s RAS features
    6. 2.6 Connectivity
      1. 2.6.1 Redundant I/O interconnect
    7. 2.7 Model configurations
      1. 2.7.1 Upgrades
      2. 2.7.2 Concurrent PU conversions
      3. 2.7.3 Model capacity identifier
      4. 2.7.4 Model capacity identifier and MSU values
      5. 2.7.5 Capacity BackUp
      6. 2.7.6 On/Off Capacity on Demand and CPs
    8. 2.8 Power and cooling
      1. 2.8.1 Power considerations
      2. 2.8.2 High-voltage DC power
      3. 2.8.3 Internal Battery Feature
      4. 2.8.4 Power capping
      5. 2.8.5 Power Estimation tool
      6. 2.8.6 Cooling requirements
    9. 2.9 Summary of z13s structure
  8. Chapter 3. Central processor complex system design
    1. 3.1 Overview
    2. 3.2 Design highlights
    3. 3.3 CPC drawer design
      1. 3.3.1 Cache levels and memory structure
      2. 3.3.2 CPC drawer interconnect topology
    4. 3.4 Processor unit design
      1. 3.4.1 Simultaneous multithreading
      2. 3.4.2 Single-instruction multiple-data
      3. 3.4.3 Out-of-order execution
      4. 3.4.4 Superscalar processor
      5. 3.4.5 Compression and cryptography accelerators on a chip
      6. 3.4.6 Decimal floating point accelerator
      7. 3.4.7 IEEE floating point
      8. 3.4.8 Processor error detection and recovery
      9. 3.4.9 Branch prediction
      10. 3.4.10 Wild branch
      11. 3.4.11 Translation lookaside buffer
      12. 3.4.12 Instruction fetching, decoding, and grouping
      13. 3.4.13 Extended Translation Facility
      14. 3.4.14 Instruction set extensions
      15. 3.4.15 Transactional Execution
      16. 3.4.16 Runtime Instrumentation
    5. 3.5 Processor unit functions
      1. 3.5.1 Overview
      2. 3.5.2 Central processors
      3. 3.5.3 Integrated Facility for Linux
      4. 3.5.4 Internal Coupling Facility
      5. 3.5.5 IBM z Integrated Information Processor
      6. 3.5.6 System assist processors
      7. 3.5.7 Reserved processors
      8. 3.5.8 Integrated firmware processor
      9. 3.5.9 Processor unit assignment
      10. 3.5.10 Sparing rules
      11. 3.5.11 Increased flexibility with z/VM mode partitions
    6. 3.6 Memory design
      1. 3.6.1 Overview
      2. 3.6.2 Main storage
      3. 3.6.3 Expanded storage
      4. 3.6.4 Hardware system area (HSA)
    7. 3.7 Logical partitioning
      1. 3.7.1 Overview
      2. 3.7.2 Storage operations
      3. 3.7.3 Reserved storage
      4. 3.7.4 Logical partition storage granularity
      5. 3.7.5 LPAR dynamic storage reconfiguration
    8. 3.8 Intelligent Resource Director
    9. 3.9 Clustering technology
      1. 3.9.1 Coupling Facility Control Code
      2. 3.9.2 Coupling Thin Interrupts
      3. 3.9.3 Dynamic CF dispatching
      4. 3.9.4 CFCC and Flash Express use
  9. Chapter 4. Central processor complex I/O system structure
    1. 4.1 Introduction to the InfiniBand and PCIe for I/O infrastructure
      1. 4.1.1 InfiniBand I/O infrastructure
      2. 4.1.2 PCIe I/O infrastructure
      3. 4.1.3 InfiniBand specifications
      4. 4.1.4 PCIe Generation 3
    2. 4.2 I/O system overview
      1. 4.2.1 Characteristics
      2. 4.2.2 Summary of supported I/O features
    3. 4.3 I/O drawer
    4. 4.4 PCIe I/O drawer
    5. 4.5 PCIe I/O drawer and I/O drawer offerings
    6. 4.6 Fanouts
      1. 4.6.1 PCIe Generation 3 fanout (FC 0173)
      2. 4.6.2 HCA2-C fanout (FC 0162)
      3. 4.6.3 Integrated Coupling Adapter (FC 0172)
      4. 4.6.4 HCA3-O (12x IFB) fanout (FC 0171)
      5. 4.6.5 HCA3-O LR (1x IFB) fanout (FC 0170)
      6. 4.6.6 Fanout considerations
    7. 4.7 I/O features (cards)
      1. 4.7.1 I/O feature card ordering information
      2. 4.7.2 Physical channel report
    8. 4.8 Connectivity
      1. 4.8.1 I/O feature support and configuration rules
      2. 4.8.2 FICON channels
      3. 4.8.3 OSA-Express5S
      4. 4.8.4 OSA-Express4S features
      5. 4.8.5 OSA-Express for ensemble connectivity
      6. 4.8.6 HiperSockets
    9. 4.9 Parallel Sysplex connectivity
      1. 4.9.1 Coupling links
      2. 4.9.2 Migration considerations
      3. 4.9.3 Pulse per second input
    10. 4.10 Cryptographic functions
      1. 4.10.1 CPACF functions (FC 3863)
      2. 4.10.2 Crypto Express5S feature (FC 0890)
    11. 4.11 Integrated firmware processor
    12. 4.12 Flash Express
      1. 4.12.1 IBM Flash Express read/write cache
    13. 4.13 10GbE RoCE Express
    14. 4.14 zEDC Express
  10. Chapter 5. Central processor complex channel subsystem
    1. 5.1 Channel subsystem
      1. 5.1.1 Multiple logical channel subsystems
      2. 5.1.2 Multiple subchannel sets
      3. 5.1.3 Channel path spanning
    2. 5.2 I/O configuration management
    3. 5.3 Channel subsystem summary
  11. Chapter 6. Cryptography
    1. 6.1 Cryptography in IBM z13 and z13s servers
    2. 6.2 Some fundamentals on cryptography
      1. 6.2.1 Modern cryptography
      2. 6.2.2 Kerckhoffs’ principle
      3. 6.2.3 Keys
      4. 6.2.4 Algorithms
    3. 6.3 Cryptography on IBM z13s servers
    4. 6.4 CP Assist for Cryptographic Functions
      1. 6.4.1 Cryptographic synchronous functions
      2. 6.4.2 CPACF protected key
    5. 6.5 Crypto Express5S
      1. 6.5.1 Cryptographic asynchronous functions
      2. 6.5.2 Crypto Express5S as a CCA coprocessor
      3. 6.5.3 Crypto Express5S as an EP11 coprocessor
      4. 6.5.4 Crypto Express5S as an accelerator
      5. 6.5.5 Management of Crypto Express5S
    6. 6.6 TKE workstation
      1. 6.6.1 Logical partition, TKE host, and TKE target
      2. 6.6.2 Optional smart card reader
      3. 6.6.3 TKE workstation with Licensed Internal Code 8.0
      4. 6.6.4 TKE workstation with Licensed Internal Code 8.1
      5. 6.6.5 TKE hardware support and migration information
    7. 6.7 Cryptographic functions comparison
    8. 6.8 Cryptographic software support
  12. Chapter 7. Software support
    1. 7.1 Operating systems summary
    2. 7.2 Support by operating system
      1. 7.2.1 z/OS
      2. 7.2.2 z/VM
      3. 7.2.3 z/VSE
      4. 7.2.4 z/TPF
      5. 7.2.5 Linux on z Systems
      6. 7.2.6 KVM for IBM z Systems
      7. 7.2.7 z13s function support summary
    3. 7.3 Support by function
      1. 7.3.1 Single system image
      2. 7.3.2 zIIP support
      3. 7.3.3 Transactional Execution
      4. 7.3.4 Maximum main storage size
      5. 7.3.5 Flash Express
      6. 7.3.6 z Enterprise Data Compression Express
      7. 7.3.7 10GbE RoCE Express
      8. 7.3.8 Large page support
      9. 7.3.9 Hardware decimal floating point
      10. 7.3.10 Up to 40 LPARs
      11. 7.3.11 Separate LPAR management of PUs
      12. 7.3.12 Dynamic LPAR memory upgrade
      13. 7.3.13 LPAR physical capacity limit enforcement
      14. 7.3.14 Capacity Provisioning Manager
      15. 7.3.15 Dynamic PU add
      16. 7.3.16 HiperDispatch
      17. 7.3.17 The 63.75-K subchannels
      18. 7.3.18 Multiple Subchannel Sets
      19. 7.3.19 Three subchannel sets
      20. 7.3.20 IPL from an alternative subchannel set
      21. 7.3.21 Modified Indirect Data Address Word facility
      22. 7.3.22 HiperSockets Completion Queue
      23. 7.3.23 HiperSockets integration with the intraensemble data network
      24. 7.3.24 HiperSockets Virtual Switch Bridge
      25. 7.3.25 HiperSockets Multiple Write Facility
      26. 7.3.26 HiperSockets IPv6
      27. 7.3.27 HiperSockets Layer 2 support
      28. 7.3.28 HiperSockets network traffic analyzer for Linux on z Systems
      29. 7.3.29 FICON Express16S
      30. 7.3.30 FICON Express8S
      31. 7.3.31 FICON Express8
      32. 7.3.32 z/OS Discovery and Auto-Configuration
      33. 7.3.33 High-performance FICON
      34. 7.3.34 Request node identification data
      35. 7.3.35 32 K subchannels for the FICON Express16S
      36. 7.3.36 Extended distance FICON
      37. 7.3.37 Platform and name server registration in FICON channel
      38. 7.3.38 FICON link incident reporting
      39. 7.3.39 FCP provides increased performance
      40. 7.3.40 N_Port ID Virtualization
      41. 7.3.41 OSA-Express5S 10-Gigabit Ethernet LR and SR
      42. 7.3.42 OSA-Express5S Gigabit Ethernet LX and SX
      43. 7.3.43 OSA-Express5S 1000BASE-T Ethernet
      44. 7.3.44 OSA-Express4S 10-Gigabit Ethernet LR and SR
      45. 7.3.45 OSA-Express4S Gigabit Ethernet LX and SX
      46. 7.3.46 OSA-Express4S 1000BASE-T Ethernet
      47. 7.3.47 Open Systems Adapter for IBM zAware
      48. 7.3.48 Open Systems Adapter for Ensemble
      49. 7.3.49 Intranode management network
      50. 7.3.50 Intraensemble data network
      51. 7.3.51 OSA-Express5S and OSA-Express4S NCP support
      52. 7.3.52 Integrated Console Controller
      53. 7.3.53 VLAN management enhancements
      54. 7.3.54 GARP VLAN Registration Protocol
      55. 7.3.55 Inbound workload queuing for OSA-Express5S and OSA-Express4S
      56. 7.3.56 Inbound workload queuing for Enterprise Extender
      57. 7.3.57 Querying and displaying an OSA configuration
      58. 7.3.58 Link aggregation support for z/VM
      59. 7.3.59 Multi-VSwitch Link Aggregation
      60. 7.3.60 QDIO data connection isolation for z/VM
      61. 7.3.61 QDIO interface isolation for z/OS
      62. 7.3.62 QDIO optimized latency mode
      63. 7.3.63 Large send for IPv6 packets
      64. 7.3.64 OSA-Express5S and OSA-Express4S checksum offload
      65. 7.3.65 Checksum offload for IPv4and IPv6 packets when in QDIO mode
      66. 7.3.66 Adapter interruptions for QDIO
      67. 7.3.67 OSA Dynamic LAN idle
      68. 7.3.68 OSA Layer 3 virtual MAC for z/OS environments
      69. 7.3.69 QDIO Diagnostic Synchronization
      70. 7.3.70 Network Traffic Analyzer
      71. 7.3.71 Program-directed re-IPL
      72. 7.3.72 Coupling over InfiniBand and Integrated Coupling Adapter
      73. 7.3.73 Dynamic I/O support for InfiniBand and ICA CHPIDs
      74. 7.3.74 Simultaneous multithreading
      75. 7.3.75 Single Instruction Multiple Data
      76. 7.3.76 Shared Memory Communication - Direct Memory Access
    4. 7.4 Cryptographic support
      1. 7.4.1 CP Assist for Cryptographic Function
      2. 7.4.2 Crypto Express5S
      3. 7.4.3 Web deliverables
      4. 7.4.4 z/OS Integrated Cryptographic Service Facility FMIDs
      5. 7.4.5 ICSF migration considerations
    5. 7.5 GDPS Virtual Appliance
    6. 7.6 z/OS migration considerations
      1. 7.6.1 General guidelines
      2. 7.6.2 Hardware configuration definition
      3. 7.6.3 Coupling links
      4. 7.6.4 Large page support
      5. 7.6.5 Capacity Provisioning Manager
      6. 7.6.6 Decimal floating point and z/OS XL C/C++ considerations
    7. 7.7 IBM z Advanced Workload Analysis Reporter (zAware)
      1. 7.7.1 z Appliance Container Infrastructure mode LPAR
    8. 7.8 Coupling facility and CFCC considerations
      1. 7.8.1 CFCC Level 21
      2. 7.8.2 Flash Express exploitation by CFCC
      3. 7.8.3 CFCC Coupling Thin Interrupts
    9. 7.9 Simultaneous multithreading
    10. 7.10 Single-instruction multiple-data
    11. 7.11 The MIDAW facility
      1. 7.11.1 MIDAW technical description
      2. 7.11.2 Extended format data sets
      3. 7.11.3 Performance benefits
    12. 7.12 IOCP
    13. 7.13 Worldwide port name tool
    14. 7.14 ICKDSF
    15. 7.15 IBM z BladeCenter Extension (zBX) Model 004 software support
      1. 7.15.1 IBM Blades
      2. 7.15.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
    16. 7.16 Software licensing
      1. 7.16.1 Software licensing considerations
      2. 7.16.2 Monthly license charge pricing metrics
      3. 7.16.3 Advanced Workload License Charges
      4. 7.16.4 Advanced Entry Workload License Charge
      5. 7.16.5 System z New Application License Charges
      6. 7.16.6 Midrange workload license charges
      7. 7.16.7 Parallel Sysplex License Charges
      8. 7.16.8 z Systems International Program License Agreement
      9. 7.16.9 zBX licensed software
    17. 7.17 References
  13. Chapter 8. System upgrades
    1. 8.1 Upgrade types
      1. 8.1.1 Overview of upgrade types
      2. 8.1.2 Terminology related to CoD for z13s systems
      3. 8.1.3 Permanent upgrades
      4. 8.1.4 Temporary upgrades
    2. 8.2 Concurrent upgrades
      1. 8.2.1 Model upgrades
      2. 8.2.2 Customer Initiated Upgrade facility
      3. 8.2.3 Summary of concurrent upgrade functions
    3. 8.3 Miscellaneous equipment specification upgrades
      1. 8.3.1 MES upgrade for processors
      2. 8.3.2 MES upgrade for memory
      3. 8.3.3 Preplanned Memory feature
      4. 8.3.4 MES upgrades for the zBX
    4. 8.4 Permanent upgrade through the CIU facility
      1. 8.4.1 Ordering
      2. 8.4.2 Retrieval and activation
    5. 8.5 On/Off Capacity on Demand
      1. 8.5.1 Overview
      2. 8.5.2 Ordering
      3. 8.5.3 On/Off CoD testing
      4. 8.5.4 Activation and deactivation
      5. 8.5.5 Termination
      6. 8.5.6 IBM z/OS capacity provisioning
    6. 8.6 Capacity for Planned Event
    7. 8.7 Capacity BackUp
      1. 8.7.1 Ordering
      2. 8.7.2 CBU activation and deactivation
      3. 8.7.3 Automatic CBU for Geographically Dispersed Parallel Sysplex
    8. 8.8 Nondisruptive upgrades
      1. 8.8.1 Processors
      2. 8.8.2 Memory
      3. 8.8.3 I/O
      4. 8.8.4 Cryptographic adapters
      5. 8.8.5 Special features
      6. 8.8.6 Concurrent upgrade considerations
    9. 8.9 Summary of capacity on-demand offerings
  14. Chapter 9. Reliability, availability, and serviceability
    1. 9.1 The RAS strategy
    2. 9.2 Availability characteristics
    3. 9.3 RAS functions
      1. 9.3.1 Unscheduled outages
      2. 9.3.2 Scheduled outages
    4. 9.4 Enhanced Driver Maintenance
    5. 9.5 RAS capability for the HMC and SE
    6. 9.6 RAS capability for zBX Model 004
      1. 9.6.1 zBX RAS and the IBM z Unified Resource Manager
      2. 9.6.2 zBX Model 004: 2458-004
    7. 9.7 Considerations for PowerHA in zBX environment
    8. 9.8 IBM z Advanced Workload Analysis Reporter
    9. 9.9 RAS capability for Flash Express
  15. Chapter 10. Environmental requirements
    1. 10.1 IBM z13s power and cooling
      1. 10.1.1 Power and I/O cabling
      2. 10.1.2 Power consumption
      3. 10.1.3 Internal Battery Feature
      4. 10.1.4 Balanced Power Plan Ahead
      5. 10.1.5 Emergency power-off
      6. 10.1.6 Cooling requirements
      7. 10.1.7 New environmental class for IBM z13s servers: ASHREA Class A3
    2. 10.2 IBM z13s physical specifications
      1. 10.2.1 Weights and dimensions
      2. 10.2.2 Four-in-one (4-in-1) bolt-down kit
    3. 10.3 IBM zBX environmental components
      1. 10.3.1 IBM zBX configurations
      2. 10.3.2 IBM zBX power components
      3. 10.3.3 IBM zBX cooling
      4. 10.3.4 IBM zBX physical specifications
    4. 10.4 Energy management
      1. 10.4.1 Power estimation tool
      2. 10.4.2 Query maximum potential power
      3. 10.4.3 System Activity Display and Monitors Dashboard
      4. 10.4.4 IBM Systems Director Active Energy Manager
      5. 10.4.5 Unified Resource Manager: Energy management
  16. Chapter 11. Hardware Management Console and Support Elements
    1. 11.1 Introduction to the HMC and SE
    2. 11.2 HMC and SE enhancements and changes
      1. 11.2.1 Driver Level 27 HMC and SE enhancements and changes
      2. 11.2.2 Rack-mounted HMC
      3. 11.2.3 New Support Elements
      4. 11.2.4 New backup options for HMCs and primary SEs
      5. 11.2.5 SE driver support with the HMC driver
      6. 11.2.6 HMC feature codes
      7. 11.2.7 Tree Style User Interface and Classic Style User Interface
    3. 11.3 HMC and SE connectivity
      1. 11.3.1 Network planning for the HMC and SE
      2. 11.3.2 Hardware prerequisite changes
      3. 11.3.3 RSF is broadband-only
      4. 11.3.4 TCP/IP Version 6 on the HMC and SE
      5. 11.3.5 Assigning addresses to the HMC and SE
    4. 11.4 Remote Support Facility
      1. 11.4.1 Security characteristics
      2. 11.4.2 RSF connections to IBM and Enhanced IBM Service Support System
      3. 11.4.3 HMC and SE remote operations
    5. 11.5 HMC and SE key capabilities
      1. 11.5.1 Central processor complex management
      2. 11.5.2 Logical partition management
      3. 11.5.3 Operating system communication
      4. 11.5.4 HMC and SE microcode
      5. 11.5.5 Monitoring
      6. 11.5.6 Capacity on demand support
      7. 11.5.7 Features on Demand support
      8. 11.5.8 Server Time Protocol support
      9. 11.5.9 NTP client and server support on the HMC
      10. 11.5.10 Security and user ID management
      11. 11.5.11 System Input/Output Configuration Analyzer on the SE and HMC
      12. 11.5.12 Automated operations
      13. 11.5.13 Cryptographic support
      14. 11.5.14 Installation support for z/VM using the HMC
      15. 11.5.15 Dynamic Partition Manager
    6. 11.6 HMC in an ensemble
      1. 11.6.1 Unified Resource Manager
      2. 11.6.2 Ensemble definition and management
      3. 11.6.3 HMC availability
      4. 11.6.4 Considerations for multiple HMCs
      5. 11.6.5 HMC browser session to a primary HMC
      6. 11.6.6 HMC ensemble topology
  17. Chapter 12. Performance
    1. 12.1 Performance information
    2. 12.2 LSPR workload suite
    3. 12.3 Fundamental components of workload capacity performance
      1. 12.3.1 Instruction path length
      2. 12.3.2 Instruction complexity
      3. 12.3.3 Memory hierarchy and memory nest
    4. 12.4 Relative nest intensity
    5. 12.5 LSPR workload categories based on relative nest intensity
    6. 12.6 Relating production workloads to LSPR workloads
    7. 12.7 Workload performance variation
      1. 12.7.1 Main performance improvement drivers with z13s
  18. Appendix A. IBM z Appliance Container Infrastructure
    1. A.1 What is zACI?
    2. A.2 Why use zACI?
    3. A.3 IBM z Systems servers and zACI
      1. 12.7.2 Example: Deploying IBM zAware
  19. Appendix B. IBM z Systems Advanced Workload Analysis Reporter (IBM zAware)
    1. B.1 Troubleshooting in complex IT environments
    2. B.2 Introducing IBM zAware
    3. B.3 Understanding IBM zAware technology
    4. B.4 IBM zAware prerequisites
      1. 12.7.3 Feature on Demand (FoD)
    5. B.5 Configuring and using IBM zAware virtual appliance
  20. Appendix C. Channel options
    1. C.1 Channel options supported on z13s servers
    2. C.2 Maximum unrepeated distance for FICON SX features
  21. Appendix D. Shared Memory Communications
    1. D.1 Shared Memory Communications overview
    2. D.2 Shared Memory Communication over RDMA
    3. D.3 Shared Memory Communications - Direct Memory Access
  22. Appendix E. IBM Dynamic Partition Manager
    1. E.1 What is IBM Dynamic Partition Manager?
    2. E.2 Why use DPM?
    3. E.3 IBM z Systems servers and DPM
    4. E.4 Setting up the DPM environment
  23. Appendix F. KVM for IBM z Systems
    1. F.1 Why KVM for IBM z Systems
    2. F.2 IBM z Systems servers and KVM
    3. F.3 Managing the KVM for IBM z Systems environment
    4. F.4 Using IBM Cloud Manager with OpenStack
  24. Appendix G. Native Peripheral Component Interconnect Express
    1. G.1 Design of native PCIe I/O adapter management
    2. G.2 Native PCIe feature plugging rules
    3. G.3 Native PCIe feature definitions
  25. Appendix H. Flash Express
    1. H.1 Flash Express overview
    2. H.2 Using Flash Express
    3. H.3 Security on Flash Express
  26. Appendix I. GDPS Virtual Appliance
    1. I.1 GDPS overview
    2. I.2 Overview of GDPS Virtual Appliance
    3. I.3 GDPS Virtual Appliance recovery scenarios
  27. Appendix J. IBM zEnterprise Data Compression Express
    1. J.1 Overview
    2. J.2 zEDC Express
    3. J.3 Software support
  28. Related publications
    1. IBM Redbooks
    2. Other publications
    3. Online resources
    4. Help from IBM
  29. Back cover