Integrated Devices for Artificial Intelligence and VLSI

5Graphene Nanoribbon for Future VLSI Applications: A Review

Himanshu Sharma

Department of ECE, Chandigarh University, Mohali, India

Abstract

The Moore law for scaling of technological nodes has led to the major advancement in chip design and functionality. With the downscaling of technological nodes, the efficiency of gate becomes insignificant compared to the interconnect performance. The reliability issue play a major role at nano-scaled technological nodes since future interconnects requires higher current density with compact cross-sectional dimensions. Formerly, copper was employed as interconnect due to high current density and less resistivity but as technology downscales below 45nm its resistance increases due to the reduction of MFP. The scaling of interconnect dimensions effects the delay time as well as power dissipation. The electronics circuit operational speed is affected by the signal delay at the output of wire. The power dissipation is also a key factor in VLSI ICs. In today’s world, everyone demands higher power standby and speed in electronic circuits. The motivation for minimizing delay in signal and power dissipation at global lengths for various technological nodes varies according to applications. The overall performance of electronic circuit depends on the product of power dissipation and delay. Both are independent parameters but to estimate actual performance of an interconnect, their product must be taken into account for elite integrated circuits. ...